soc/interconnect/stream/SyncFIFO: expose fifo level

litex/soc/interconnect/stream.py

@@ -113,6 +113,7 @@ class SyncFIFO(_FIFOWrapper):
             self,
             fifo.SyncFIFOBuffered if buffered else fifo.SyncFIFO,
             layout, depth)
+        self.level = self.fifo.level
 
 
 class AsyncFIFO(_FIFOWrapper):

litex/soc/interconnect/stream_packet.py

@@ -379,6 +379,6 @@ class Buffer(Module):
         # compute almost full
         if almost_full is not None:
             self.almost_full = Signal()
-            self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)
+            self.comb += self.almost_full.eq(data_fifo.level > almost_full)
 
 # XXX