Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

Merge pull request #198 from TomKeddie/tomk_20190610_artyspi

Browse source 
boards/arty : Add directly connected spi clk pin
This commit is contained in:
enjoy-digital 2019-06-11 15:50:02 +02:00 committed by GitHub
commit 33d7cc5fc8
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 4 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
litex/boards/platforms/arty.py
View file

@ -79,13 +79,15 @@ _io = [
IOStandard("LVCMOS33"),
),
("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
("spiflash4x", 0,
Subsignal("cs_n", Pins("L13")),
Subsignal("clk", Pins("L16")),
Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
IOStandard("LVCMOS33")
),
("spiflash", 0, # clock needs to be accessed through STARTUPE2
("spiflash", 0,
Subsignal("cs_n", Pins("L13")),
Subsignal("clk", Pins("L16")),
Subsignal("mosi", Pins("K17")),
Subsignal("miso", Pins("K18")),
Subsignal("wp", Pins("L14")),