gen/build: use verilog 2001-style synthesis attributes for vivado (will need rework)
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@ -44,7 +44,7 @@ def settings(path, ver=None, sub=None):
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class XilinxNoRetimingImpl(Module):
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def __init__(self, reg):
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self.specials += SynthesisDirective("attribute register_balancing of {r} is no", r=reg)
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reg.attribute += " OPTIMIZE =\"OFF\"," # XXX "register balancing is no" equivalent?
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class XilinxNoRetiming:
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@ -52,12 +52,11 @@ class XilinxNoRetiming:
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def lower(dr):
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return XilinxNoRetimingImpl(dr.reg)
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class XilinxMultiRegImpl(MultiRegImpl):
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def __init__(self, *args, **kwargs):
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MultiRegImpl.__init__(self, *args, **kwargs)
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self.specials += [SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
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for r in self.regs]
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for reg in self.regs:
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reg.attribute += " SHIFT_EXTRACT=\"NO\", ASYNC_REG=\"TRUE\","
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class XilinxMultiReg:
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@ -310,7 +310,7 @@ class Signal(_Value):
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defaults to 0) and `max` (exclusive, defaults to 2).
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related : Signal or None
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"""
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def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None, related=None):
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def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None, related=None, attribute=""):
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from litex.gen.fhdl.bitcontainer import bits_for
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_Value.__init__(self)
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@ -339,6 +339,7 @@ class Signal(_Value):
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self.name_override = name_override
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self.backtrace = _tracer.trace_back(name)
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self.related = related
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self.attribute = attribute
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def __setattr__(self, k, v):
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if k == "reset":
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@ -524,7 +525,7 @@ class Case(_Statement):
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for k, v in cases.items():
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if isinstance(k, (bool, int)):
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k = Constant(k)
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if (not isinstance(k, Constant)
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if (not isinstance(k, Constant)
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and not (isinstance(k, str) and k == "default")):
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raise TypeError("Case object is not a Migen constant")
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if not isinstance(v, _collections.Iterable):
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@ -196,13 +196,16 @@ def _printheader(f, ios, name, ns,
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r += "\tinput " + _printsig(ns, sig)
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r += "\n);\n\n"
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for sig in sorted(sigs - ios, key=lambda x: x.duid):
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attributes = ""
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if sig.attribute != "":
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attributes = "(*" + sig.attribute[:-1] + "*) "
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if sig in wires:
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r += "wire " + _printsig(ns, sig) + ";\n"
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r += attributes + "wire " + _printsig(ns, sig) + ";\n"
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else:
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if reg_initialization:
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r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
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r += attributes + "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
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else:
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r += "reg " + _printsig(ns, sig) + ";\n"
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r += attributes + "reg " + _printsig(ns, sig) + ";\n"
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r += "\n"
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return r
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