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backwards compatibility with python3.7

This commit is contained in:
David Jablonski 2024-12-21 12:48:27 +01:00
parent 57333ee6c1
commit 3601b71584
2 changed files with 3 additions and 2 deletions
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3
litex/soc/cores/clock/xilinx_usp.py
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@ -143,7 +143,8 @@ class USPMMCM(XilinxClocking):
dividers = list(clkdiv_range(*self.clkout_divide_range)) dividers = list(clkdiv_range(*self.clkout_divide_range))
# Add specific range dividers if they exist # Add specific range dividers if they exist
if specific_div_range := getattr(self, f"clkout{n}_divide_range", None): specific_div_range = getattr(self, f"clkout{n}_divide_range", None)
if specific_div_range:
dividers.extend(clkdiv_range(*specific_div_range)) dividers.extend(clkdiv_range(*specific_div_range))
# For clkout0, CLKOUT[0]_DIVIDE_F also has range 2.0 to 128.0 with step 0.125 # For clkout0, CLKOUT[0]_DIVIDE_F also has range 2.0 to 128.0 with step 0.125

2
litex/tools/litex_json2dts_linux.py
View File

@ -100,7 +100,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
# Clocks --------------------------------------------------------------------------------------- # Clocks ---------------------------------------------------------------------------------------
for c in [c for c in d["constants"].keys() if c.endswith("config_clock_frequency")]: for c in [c for c in d["constants"].keys() if c.endswith("config_clock_frequency")]:
name = c.removesuffix("config_clock_frequency") + "sys_clk" name = c[:len(c) - len("config_clock_frequency")] + "sys_clk"
dts += """ dts += """
{name}: clock-{freq} {{ {name}: clock-{freq} {{
compatible = "fixed-clock"; compatible = "fixed-clock";