backwards compatibility with python3.7
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@ -143,7 +143,8 @@ class USPMMCM(XilinxClocking):
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dividers = list(clkdiv_range(*self.clkout_divide_range))
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# Add specific range dividers if they exist
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if specific_div_range := getattr(self, f"clkout{n}_divide_range", None):
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specific_div_range = getattr(self, f"clkout{n}_divide_range", None)
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if specific_div_range:
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dividers.extend(clkdiv_range(*specific_div_range))
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# For clkout0, CLKOUT[0]_DIVIDE_F also has range 2.0 to 128.0 with step 0.125
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@ -100,7 +100,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
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# Clocks ---------------------------------------------------------------------------------------
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for c in [c for c in d["constants"].keys() if c.endswith("config_clock_frequency")]:
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name = c.removesuffix("config_clock_frequency") + "sys_clk"
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name = c[:len(c) - len("config_clock_frequency")] + "sys_clk"
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dts += """
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{name}: clock-{freq} {{
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compatible = "fixed-clock";
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