Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter)

This commit is contained in:
Florent Kermarrec 2015-03-09 12:45:46 +01:00
parent 5dbd8af4be
commit 360c849f21
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
misoclib/com/liteeth/mac/frontend/sram.py
View File

@ -69,10 +69,10 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
self.submodules += fsm self.submodules += fsm
fsm.act("IDLE", fsm.act("IDLE",
inc_cnt.eq(sink.stb),
If(sink.stb & sink.sop, If(sink.stb & sink.sop,
ongoing.eq(1),
If(fifo.sink.ack, If(fifo.sink.ack,
ongoing.eq(1),
inc_cnt.eq(1),
NextState("WRITE") NextState("WRITE")
) )
) )