liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter)

2015-03-09 12:45:46 +01:00 · 2015-03-09 12:45:46 +01:00 · 360c849f21
parent 5dbd8af4be
commit 360c849f21
1 changed files with 2 additions and 2 deletions
--- a/misoclib/com/liteeth/mac/frontend/sram.py
+++ b/misoclib/com/liteeth/mac/frontend/sram.py
@ -69,10 +69,10 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
 		self.submodules += fsm

 		fsm.act("IDLE",
-			inc_cnt.eq(sink.stb),
 			If(sink.stb & sink.sop,
-				ongoing.eq(1),
 				If(fifo.sink.ack,
+					ongoing.eq(1),
+					inc_cnt.eq(1),
 					NextState("WRITE")
 				)
 			)