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soc/add_sdram: Fix typo when removing Rocket specific hardcoding.

This commit is contained in:
Florent Kermarrec 2022-02-12 21:47:08 +01:00
parent dff33885de
commit 378c430dd0
1 changed files with 1 additions and 1 deletions
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2
litex/soc/integration/soc.py
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@ -1366,7 +1366,7 @@ class LiteXSoC(SoC):
else: else:
self.logger.info("Converting MEM data width: {} to {} via Wishbone".format( self.logger.info("Converting MEM data width: {} to {} via Wishbone".format(
port.data_width, port.data_width,
self.mem_bus.data_width)) mem_bus.data_width))
# FIXME: Replace WB data-width converter with native AXI converter. # FIXME: Replace WB data-width converter with native AXI converter.
mem_wb = wishbone.Interface( mem_wb = wishbone.Interface(
data_width = self.cpu.mem_axi.data_width, data_width = self.cpu.mem_axi.data_width,