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cores/dma/WishboneDMAWriter: Add ready_on_idle parameter and set it to 1 by default. 

This allows controlling ready behavior on idle state.
This commit is contained in:
Florent Kermarrec 2022-09-14 10:02:07 +02:00
parent 0adb604c97
commit 3cd4a3830c
1 changed files with 2 additions and 1 deletions
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3
litex/soc/cores/dma.py
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@ -155,7 +155,7 @@ class WishboneDMAWriter(Module, AutoCSR):
if with_csr:
self.add_csr()
def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0, ready_on_idle=1):
self._sink = self.sink
self.sink = stream.Endpoint([("data", self.bus.data_width)])
@ -182,6 +182,7 @@ class WishboneDMAWriter(Module, AutoCSR):
self.submodules += fsm
self.comb += fsm.reset.eq(~self._enable.storage)
fsm.act("IDLE",
self.sink.ready.eq(ready_on_idle),
NextValue(offset, 0),
NextState("RUN"),
)