Merge pull request #1423 from zyp/improve_dma

Improve DMA
2022-09-14 09:57:43 +02:00 · 2022-09-14 09:57:43 +02:00 · 0adb604c97
parent 89bb688500 3c4c12a72f
commit 0adb604c97
1 changed files with 1 additions and 2 deletions
--- a/litex/soc/cores/dma.py
+++ b/litex/soc/cores/dma.py
@ -182,13 +182,12 @@ class WishboneDMAWriter(Module, AutoCSR):
        self.submodules += fsm
        self.comb += fsm.reset.eq(~self._enable.storage)
        fsm.act("IDLE",
-            self.sink.ready.eq(1),
            NextValue(offset, 0),
            NextState("RUN"),
        )
        fsm.act("RUN",
            self._sink.valid.eq(self.sink.valid),
-            self._sink.last.eq(offset == (length - 1)),
+            self._sink.last.eq(self.sink.last | (offset + 1 == length)),
            self._sink.address.eq(base + offset),
            self._sink.data.eq(self.sink.data),
            self.sink.ready.eq(self._sink.ready),