cores/dma/WishboneDMAWriter: Add ready_on_idle parameter and set it to 1 by default.
This allows controlling ready behavior on idle state.
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@ -155,7 +155,7 @@ class WishboneDMAWriter(Module, AutoCSR):
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if with_csr:
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if with_csr:
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self.add_csr()
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self.add_csr()
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def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
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def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0, ready_on_idle=1):
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self._sink = self.sink
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self._sink = self.sink
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self.sink = stream.Endpoint([("data", self.bus.data_width)])
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self.sink = stream.Endpoint([("data", self.bus.data_width)])
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@ -182,6 +182,7 @@ class WishboneDMAWriter(Module, AutoCSR):
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self.submodules += fsm
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self.submodules += fsm
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self.comb += fsm.reset.eq(~self._enable.storage)
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self.comb += fsm.reset.eq(~self._enable.storage)
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fsm.act("IDLE",
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fsm.act("IDLE",
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self.sink.ready.eq(ready_on_idle),
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NextValue(offset, 0),
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NextValue(offset, 0),
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NextState("RUN"),
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NextState("RUN"),
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)
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)
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