Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

integration/soc: data_width_convert: Inherit more bus properties 

For data_width converter we need to ensure that adapted interface
have same properties as it's parent interface, so that id and user
signals for AXI will be propagated properly from parent to adapted
interface.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
This commit is contained in:
Jiaxun Yang 2024-06-22 17:54:41 +01:00
parent dd01a87653
commit 3d530e0b59
No known key found for this signature in database
GPG Key ID: 43710C7DD77729C3
1 changed files with 18 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
litex/soc/integration/soc.py
View File

@ -346,11 +346,24 @@ class SoCBusHandler(LiteXModule):
axi.AXILiteInterface : axi.AXILiteConverter,
axi.AXIInterface : axi.AXIConverter,
}[interface_cls]
adapted_interface = interface_cls(
data_width = self.data_width,
address_width = self.address_width,
addressing = interface.addressing,
)
args = {
'data_width': self.data_width,
'address_width': self.address_width,
'addressing': interface.addressing,
'bursting' : interface.bursting,
}
if isinstance(interface, axi.AXIInterface):
args.update({
'version' : interface.version,
'id_width': interface.id_width,
'aw_user_width': interface.aw.user_width,
'w_user_width': interface.w.user_width,
'b_user_width': interface.b.user_width,
'ar_user_width': interface.ar.user_width,
'r_user_width': interface.r.user_width,
})
adapted_interface = interface_cls(**args)
if direction == "m2s":
master, slave = interface, adapted_interface
elif direction == "s2m":