Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Change SDRAM region to RWX

This commit is contained in:
Christian Klarhorst 2022-08-30 16:22:29 +02:00
parent 76c0754d1e
commit 3e42133abd
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
litex/soc/integration/soc.py
View File

@ -1461,7 +1461,8 @@ class LiteXSoC(SoC):
# Add SDRAM region. # Add SDRAM region.
main_ram_region = SoCRegion(origin=self.mem_map.get("main_ram", origin), main_ram_region = SoCRegion(origin=self.mem_map.get("main_ram", origin),
size=sdram_size) size=sdram_size,
mode="rwx")
self.bus.add_region("main_ram", main_ram_region) self.bus.add_region("main_ram", main_ram_region)
# Add CPU's direct memory buses (if not already declared) ---------------------------------- # Add CPU's direct memory buses (if not already declared) ----------------------------------