Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

check calculated PLL frequencies against user's values

This commit is contained in:
Franck Jullien 2021-12-13 14:42:33 +01:00
parent eafee9dac5
commit 40c001d522
1 changed files with 10 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
litex/build/efinix/ifacewriter.py
View File

@ -220,13 +220,19 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
cmd += 'print("#### {} ####")\n'.format(name)
cmd += 'clksrc_info = design.trace_ref_clock("{}", block_type="PLL")\n'.format(name)
cmd += 'pprint.pprint(clksrc_info)\n'
cmd += 'clock_source_prop = ["REFCLK_SOURCE", "CORE_CLK_PIN", "EXT_CLK", "CLKOUT1_EN", "CLKOUT2_EN","REFCLK_FREQ", "RESOURCE"]\n'
cmd += 'clock_source_prop += ["CLKOUT0_FREQ", "CLKOUT1_FREQ", "CLKOUT2_FREQ"]\n'
cmd += 'clock_source_prop += ["CLKOUT0_PHASE", "CLKOUT1_PHASE", "CLKOUT2_PHASE"]\n'
cmd += 'clock_source_prop = ["REFCLK_SOURCE", "CORE_CLK_PIN", "EXT_CLK", "REFCLK_FREQ", "RESOURCE"]\n'
for i, clock in enumerate(block["clk_out"]):
cmd += 'clock_source_prop += ["CLKOUT{}_FREQ", "CLKOUT{}_PHASE", "CLKOUT{}_EN"]\n'.format(i, i, i)
cmd += 'prop_map = design.get_property("{}", clock_source_prop, block_type="PLL")\n'.format(name)
cmd += 'pprint.pprint(prop_map)\n'
cmd += "# ---------- END PLL {} ---------\n\n".format(name)
for i, clock in enumerate(block["clk_out"]):
cmd += '\nfreq = float(prop_map["CLKOUT{}_FREQ"])\n'.format(i)
cmd += 'if freq != {}:\n'.format(clock[1]/1e6)
cmd += ' print("ERROR: CLKOUT{} configured for {}MHz is {{}}MHz".format(freq))\n'.format(i, clock[1]/1e6)
cmd += ' exit("PLL ERROR")\n'
cmd += "\n#---------- END PLL {} ---------\n\n".format(name)
return cmd
def generate(self, partnumber):