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cores/uart: Fix refactoring typo (tick is a 1-bit Signal), thanks @tnt.

This commit is contained in:
Florent Kermarrec 2021-06-20 08:58:45 +02:00
parent e7d04a2d1b
commit 4c8184fbb6
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/uart.py
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@ -42,7 +42,7 @@ class RS232ClkPhaseAccum(Module):
def __init__(self, tuning_word, mode="tx"): def __init__(self, tuning_word, mode="tx"):
assert mode in ["tx", "rx"] assert mode in ["tx", "rx"]
self.enable = Signal() self.enable = Signal()
self.tick = Signal(32) self.tick = Signal()
# # # # # #