cores/uart: Fix refactoring typo (tick is a 1-bit Signal), thanks @tnt.

2021-06-20 08:58:45 +02:00 · 2021-06-20 08:58:45 +02:00 · 4c8184fbb6
parent e7d04a2d1b
commit 4c8184fbb6
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@ -42,7 +42,7 @@ class RS232ClkPhaseAccum(Module):
    def __init__(self, tuning_word, mode="tx"):
        assert mode in ["tx", "rx"]
        self.enable = Signal()
-        self.tick   = Signal(32)
+        self.tick   = Signal()

        # # #