set default l2 ways to 4

2024-04-08 17:16:15 +02:00 · 2024-04-08 17:16:15 +02:00 · 555f89c22a
parent 9654b40864
commit 555f89c22a
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/cpu/vexiiriscv/core.py
+++ b/litex/soc/cores/cpu/vexiiriscv/core.py
@ -50,7 +50,7 @@ class VexiiRiscv(CPU):
    internal_bus_width = 32
    litedram_width   = 32
    l2_bytes         = 0
-    l2_ways          = 0
+    l2_ways          = 4
    with_fpu         = False
    with_rvc         = False
    with_rvm         = False