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CHANGES: Update.

This commit is contained in:
Florent Kermarrec 2023-09-01 12:40:03 +02:00
parent f473261bc6
commit 57faa9102f
1 changed files with 3 additions and 0 deletions
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@ -61,6 +61,9 @@
- soc/interconnect/stream : Added pipe_valid/pipe_ready parameters to BufferizeEndpoints. - soc/interconnect/stream : Added pipe_valid/pipe_ready parameters to BufferizeEndpoints.
- soc/cores/clock : Added initial GW5A support. - soc/cores/clock : Added initial GW5A support.
- build/efinix : Added initial EfinixDDROutput/Input and simplified IOs exclusion. - build/efinix : Added initial EfinixDDROutput/Input and simplified IOs exclusion.
- soc/interconnect : Improved DMA Bus to use the same Bus Standard than the CPU DMA Bus.
- liteeth/phy : Added Artix7 2500BASE-X PHY.
- liteeth/phy : Added Gowin Arora V RGMII PHY (GW5RGMII).
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