cpu/vexii add git
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@ -129,8 +129,8 @@ class VexiiRiscv(CPU):
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def args_read(args):
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def args_read(args):
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print(args)
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print(args)
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# if args.update_repo != "no":
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if args.update_repo != "no":
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# NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "main", "ec3ee4dc" if args.update_repo=="recommended" else None)
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "main", "af662e86" if args.update_repo=="recommended" else None)
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