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update naxriscv comments

This commit is contained in:
Christian Klarhorst 2022-09-09 13:19:36 +02:00
parent 14160ce7e3
commit 6367fc6cab
1 changed files with 5 additions and 5 deletions
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10
litex/soc/cores/cpu/naxriscv/core.py
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@ -471,11 +471,11 @@ class NaxRiscv(CPU):
# Generate memory map from CPU perspective # Generate memory map from CPU perspective
# naxriscv modes: # naxriscv modes:
# r,w : regular memory load/store # r,w,x,c : readable, writeable, executable, caching allowed
# i,o : peripheral memory load/store # io : IO region (Implies P bus, preserve memory order, no dcache)
# x : instruction fetchable (execute) # naxriscv bus:
# litex modes: # p : peripheral
# rwx : load, store, execute (everything is peripheral per default) # m : memory
NaxRiscv.memory_regions = [] NaxRiscv.memory_regions = []
for name, region in self.soc.bus.io_regions.items(): for name, region in self.soc.bus.io_regions.items():
NaxRiscv.memory_regions.append( (region.origin, region.size, "io", "p") ) # IO is only allowed on the p bus NaxRiscv.memory_regions.append( (region.origin, region.size, "io", "p") ) # IO is only allowed on the p bus