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soc/add_uart: Fix stub behavior (sink/source swap), thanks @zyp.

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Florent Kermarrec 2023-07-26 12:26:16 +02:00
parent 0f1fdea893
commit 66b44ecd60
2 changed files with 2 additions and 1 deletions
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1
CHANGES.md
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@ -12,6 +12,7 @@
- liteeth/core/icmp : Fixed length check on LiteEthICMPEcho before passing data to buffer. - liteeth/core/icmp : Fixed length check on LiteEthICMPEcho before passing data to buffer.
- LiteXModule/CSR : Fixed CSR collection order causing CSR clock domain to be changed. - LiteXModule/CSR : Fixed CSR collection order causing CSR clock domain to be changed.
- litepcie/US(P) : Fixed root cause of possible MSI deadlock. - litepcie/US(P) : Fixed root cause of possible MSI deadlock.
- soc/add_uart : Fixed stub behavior (sink/source swap).
[> Added [> Added
-------- --------

2
litex/soc/integration/soc.py
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@ -1394,7 +1394,7 @@ class LiteXSoC(SoC):
# Stub / Stream. # Stub / Stream.
elif uart_name in ["stub", "stream"]: elif uart_name in ["stub", "stream"]:
uart = UART(tx_fifo_depth=0, rx_fifo_depth=0) uart = UART(tx_fifo_depth=0, rx_fifo_depth=0)
self.comb += uart.sink.ready.eq(uart_name == "stub") self.comb += uart.source.ready.eq(uart_name == "stub")
# UARTBone. # UARTBone.
elif uart_name in ["uartbone"]: elif uart_name in ["uartbone"]: