mac: fix missing core csr generation
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@ -23,7 +23,7 @@ class LiteEthMAC(Module, AutoCSR):
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self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
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self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
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self.comb += Port.connect(self.interface, self.core)
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self.comb += Port.connect(self.interface, self.core)
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self.ev, self.bus = self.interface.sram.ev, self.interface.bus
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self.ev, self.bus = self.interface.sram.ev, self.interface.bus
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self.csrs = self.interface.get_csrs()
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self.csrs = self.interface.get_csrs() + self.core.get_csrs()
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elif interface == "dma":
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elif interface == "dma":
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raise NotImplementedError
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raise NotImplementedError
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else:
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else:
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