read/write seems OK with CommandGenerator
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5e513c25c2
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@ -215,6 +215,13 @@ class CommandGenerator(Module, AutoCSR):
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NextState("WAIT_WRITE_ACK")
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)
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)
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self.sync += [
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If(fsm.ongoing("IDLE"),
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cnt.eq(0)
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).Elif(sata_con.sink.stb & sata_con.sink.stb,
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cnt.eq(cnt+1)
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)
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]
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fsm.act("WAIT_WRITE_ACK",
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# XXX: add check of success / failed
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If(sata_con.source.stb & sata_con.source.eop,
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@ -312,16 +319,16 @@ class TestDesign(UART2WB, AutoCSR):
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self.sata_con.sink.read,
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self.sata_con.sink.identify,
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#self.sata_con.source.stb,
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#self.sata_con.source.sop,
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#self.sata_con.source.eop,
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#self.sata_con.source.ack,
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#self.sata_con.source.write,
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#self.sata_con.source.read,
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#self.sata_con.source.identify,
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#self.sata_con.source.success,
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#self.sata_con.source.failed,
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#self.sata_con.source.data,
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self.sata_con.source.stb,
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self.sata_con.source.sop,
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self.sata_con.source.eop,
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self.sata_con.source.ack,
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self.sata_con.source.write,
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self.sata_con.source.read,
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self.sata_con.source.identify,
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self.sata_con.source.success,
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self.sata_con.source.failed,
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self.sata_con.source.data,
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#self.sata_con.link.source.stb,
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#self.sata_con.link.source.sop,
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@ -337,19 +344,19 @@ class TestDesign(UART2WB, AutoCSR):
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#self.sata_con.link.rx.scrambler.sink.d,
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#self.sata_con.link.rx.scrambler.sink.error,
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self.sata_con.link.rx.scrambler.sink.stb,
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self.sata_con.link.rx.scrambler.sink.sop,
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self.sata_con.link.rx.scrambler.sink.eop,
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self.sata_con.link.rx.scrambler.sink.ack,
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self.sata_con.link.rx.scrambler.sink.d,
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self.sata_con.link.rx.scrambler.sink.error,
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#self.sata_con.link.rx.crc.sink.stb,
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#self.sata_con.link.rx.crc.sink.sop,
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#self.sata_con.link.rx.crc.sink.eop,
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#self.sata_con.link.rx.crc.sink.ack,
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#self.sata_con.link.rx.crc.sink.d,
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#self.sata_con.link.rx.crc.sink.error,
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self.sata_con.link.rx.scrambler.source.stb,
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self.sata_con.link.rx.scrambler.source.sop,
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self.sata_con.link.rx.scrambler.source.eop,
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self.sata_con.link.rx.scrambler.source.ack,
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self.sata_con.link.rx.scrambler.source.d,
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self.sata_con.link.rx.scrambler.source.error,
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self.sata_con.link.rx.crc.source.stb,
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self.sata_con.link.rx.crc.source.sop,
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self.sata_con.link.rx.crc.source.eop,
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self.sata_con.link.rx.crc.source.ack,
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self.sata_con.link.rx.crc.source.d,
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self.sata_con.link.rx.crc.source.error,
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self.command_tx_fsm_state,
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self.transport_tx_fsm_state,
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@ -8,16 +8,19 @@ wb.open()
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regs = wb.regs
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###
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#trigger0 = mila.sata_con_sink_payload_identify_o*1
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#mask0 = mila.sata_con_sink_payload_identify_m
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cond = {
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#"sata_phy_source_source_payload_data" : primitives["R_RDY"],
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#"sata_phy_source_source_payload_data" : primitives["R_OK"],
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"sata_phy_source_source_payload_data" : primitives["X_RDY"],
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}
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#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"]
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#mask0 = mila.sata_phy_source_source_payload_data_m
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trigger = 0
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mask = 0
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for k, v in cond.items():
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trigger |= getattr(mila, k+"_o")*v
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mask |= getattr(mila, k+"_m")
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trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["X_RDY"]
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mask0 = mila.sata_phy_source_source_payload_data_m
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mila.prog_term(port=0, trigger=trigger0, mask=mask0)
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mila.prog_term(port=0, trigger=trigger, mask=mask)
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mila.prog_sum("term")
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# Trigger / wait / receive
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@ -8,16 +8,20 @@ wb.open()
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regs = wb.regs
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###
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#trigger0 = mila.sata_con_sink_payload_read_o*1
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#mask0 = mila.sata_con_sink_payload_read_m
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cond = {
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#"sata_phy_source_source_payload_data" : primitives["R_RDY"],
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#"sata_phy_source_source_payload_data" : primitives["R_OK"],
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#"sata_phy_source_source_payload_data" : primitives["X_RDY"],
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"sata_con_source_source_stb" : 1,
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}
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#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"]
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#mask0 = mila.sata_phy_source_source_payload_data_m
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trigger = 0
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mask = 0
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for k, v in cond.items():
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trigger |= getattr(mila, k+"_o")*v
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mask |= getattr(mila, k+"_m")
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trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["X_RDY"]
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mask0 = mila.sata_phy_source_source_payload_data_m
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mila.prog_term(port=0, trigger=trigger0, mask=mask0)
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mila.prog_term(port=0, trigger=trigger, mask=mask)
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mila.prog_sum("term")
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# Trigger / wait / receive
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@ -8,16 +8,20 @@ wb.open()
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regs = wb.regs
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###
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#trigger0 = mila.sata_con_sink_payload_write_o*1
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#mask0 = mila.sata_con_sink_payload_write_m
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cond = {
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#"sata_phy_source_source_payload_data" : primitives["R_RDY"],
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#"sata_phy_source_source_payload_data" : primitives["R_OK"],
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#"sata_phy_source_source_payload_data" : primitives["X_RDY"],
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"sata_con_source_source_stb" : 1,
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}
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#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_RDY"]
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#mask0 = mila.sata_phy_source_source_payload_data_m
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trigger = 0
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mask = 0
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for k, v in cond.items():
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trigger |= getattr(mila, k+"_o")*v
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mask |= getattr(mila, k+"_m")
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trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"]
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mask0 = mila.sata_phy_source_source_payload_data_m
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mila.prog_term(port=0, trigger=trigger0, mask=mask0)
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mila.prog_term(port=0, trigger=trigger, mask=mask)
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mila.prog_sum("term")
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# Trigger / wait / receive
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