Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

tools/litex_sim: Add boot to main_ram when sdram_init contents provided.

This commit is contained in:
Florent Kermarrec 2021-02-25 09:10:26 +01:00
parent 8f5d2ba27f
commit 6e883b4513
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/tools/litex_sim.py
View File

@ -448,7 +448,7 @@ def main():
trace_reset_on = trace_start > 0 or trace_end > 0, trace_reset_on = trace_start > 0 or trace_end > 0,
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness), sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness),
**soc_kwargs) **soc_kwargs)
if args.ram_init is not None: if args.ram_init is not None or args.sdram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000) soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
if args.with_ethernet: if args.with_ethernet:
for i in range(4): for i in range(4):