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tools: litex_gen: fix missing UART pins

This commit is contained in:
Jan Kowalewski 2020-02-25 14:24:29 +01:00
parent 9521f2ff80
commit 75b000a32f
1 changed files with 9 additions and 0 deletions
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9
litex/tools/litex_gen.py
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@ -49,6 +49,15 @@ class LiteXCore(SoCMini):
platform = Platform(_io) platform = Platform(_io)
# UART
if kwargs["with_uart"]:
platform.add_extension([
("serial", 0,
Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)),
)
])
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst")) self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst"))