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Merge branch 'master' into vexriscv_smp

This commit is contained in:
Dolu1990 2020-07-28 19:11:54 +02:00
parent d284dfbea9 0696b409ab
commit 789a70e7c8
3 changed files with 3 additions and 4 deletions
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1
CHANGES
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@ -27,6 +27,7 @@
- Revert to a single crt0 (avoid ctr/xip variants).
- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
- Add AXI-Lite bus standard support.
- Add VexRiscv SMP CPU support.
[> API changes/Deprecation
--------------------------

4
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -12,10 +12,7 @@ from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import *
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
from litedram.common import LiteDRAMNativePort
import os
import os.path
CPU_VARIANTS = {
@ -257,6 +254,7 @@ class VexRiscvSMP(CPU):
)
]
from litedram.common import LiteDRAMNativePort
if "mp" in variant:
ncpus = int(variant[-2]) # FIXME
for n in range(ncpus):

2
litex_setup.py
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@ -46,7 +46,7 @@ repos = [
("pythondata-cpu-picorv32", ("https://github.com/litex-hub/", False, True, None)),
("pythondata-cpu-serv", ("https://github.com/litex-hub/", False, True, None)),
("pythondata-cpu-vexriscv", ("https://github.com/litex-hub/", False, True, None)),
("pythondata-cpu-vexriscv_smp",("https://github.com/litex-hub/", True, True, None)),
("pythondata-cpu-vexriscv-smp",("https://github.com/litex-hub/", True, True, None)),
("pythondata-cpu-rocket", ("https://github.com/litex-hub/", False, True, None)),
("pythondata-cpu-minerva", ("https://github.com/litex-hub/", False, True, None)),
("pythondata-cpu-microwatt", ("https://github.com/litex-hub/", False, True, 0xba76652)),