soc/cores/hyperbus: Directly specify default sys_clk_freq in __init__.
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@ -44,7 +44,7 @@ class HyperRAM(LiteXModule):
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pads (Record) : Platform pads of HyperRAM.
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pads (Record) : Platform pads of HyperRAM.
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bus (wishbone.Interface) : Wishbone Interface.
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bus (wishbone.Interface) : Wishbone Interface.
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"""
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"""
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def __init__(self, pads, latency=6, latency_mode="variable", sys_clk_freq=None, with_csr=True):
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def __init__(self, pads, latency=6, latency_mode="variable", sys_clk_freq=10e6, with_csr=True):
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self.pads = pads
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self.pads = pads
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self.bus = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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self.bus = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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@ -128,8 +128,6 @@ class HyperRAM(LiteXModule):
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raise ValueError
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raise ValueError
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# Burst Timer ------------------------------------------------------------------------------
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# Burst Timer ------------------------------------------------------------------------------
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if sys_clk_freq is None:
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sys_clk_freq = 10e6 # Defaults to 10MHz if not specified.
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self.burst_timer = burst_timer = WaitTimer(sys_clk_freq * self.tCSM)
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self.burst_timer = burst_timer = WaitTimer(sys_clk_freq * self.tCSM)
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# Clock Generation (sys_clk/4) -------------------------------------------------------------
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# Clock Generation (sys_clk/4) -------------------------------------------------------------
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