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cores/clock/xilinx_s6: Remove power_down (no i_PWRDWN input on PLL_ADV).

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This commit is contained in:
Florent Kermarrec 2021-09-02 15:12:16 +02:00
parent 8c50366d15
commit 7bd06d178f
1 changed files with 0 additions and 1 deletions
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litex/soc/cores/clock/xilinx_s6.py
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@ -37,7 +37,6 @@ class S6PLL(XilinxClocking):
p_BANDWIDTH = "OPTIMIZED",
p_COMPENSATION = "INTERNAL",
i_RST = self.reset,
i_PWRDWN = self.power_down,
o_LOCKED = self.locked,
# VCO.