cores/clock/xilinx_s6: Remove power_down (no i_PWRDWN input on PLL_ADV).

2021-09-02 15:12:16 +02:00 · 2021-09-02 15:12:16 +02:00 · 7bd06d178f
parent 8c50366d15
commit 7bd06d178f
1 changed files with 0 additions and 1 deletions
--- a/litex/soc/cores/clock/xilinx_s6.py
+++ b/litex/soc/cores/clock/xilinx_s6.py
@ -37,7 +37,6 @@ class S6PLL(XilinxClocking):
            p_BANDWIDTH      = "OPTIMIZED",
            p_COMPENSATION   = "INTERNAL",
            i_RST            = self.reset,
-            i_PWRDWN         = self.power_down,
            o_LOCKED         = self.locked,

            # VCO.