Named buses

migen/bus/csr.py

@@ -9,12 +9,12 @@ _desc = [
 ]
 
 class Master(Simple):
-	def __init__(self):
+	def __init__(self, name=""):
-		Simple.__init__(self, _desc, False)
+		Simple.__init__(self, _desc, False, name)
 
 class Slave(Simple):
-	def __init__(self):
+	def __init__(self, name=""):
-		Simple.__init__(self, _desc, True)
+		Simple.__init__(self, _desc, True, name)
 
 class Interconnect:
 	def __init__(self, master, slaves):

migen/bus/simple.py

@@ -5,7 +5,7 @@ from migen.fhdl import structure as f
 # 1) string: name
 # 2) int: width
 class Simple():
-	def __init__(self, desc, slave):
+	def __init__(self, desc, slave, name):
 		for signal in desc:
 			if signal[0] ^ slave:
 				suffix = "_o"
@@ -13,5 +13,7 @@ class Simple():
 				suffix = "_i"
 			modules = self.__module__.split('.')
 			busname = modules[len(modules)-1]
+			if name:
+				busname += "_" + name
 			signame = signal[1]+suffix
-			setattr(self, signame, f.Signal(f.BV(signal[2]), busname+"_"+signame))
+			setattr(self, signame, f.Signal(f.BV(signal[2]), busname + "_" + signame))

migen/bus/wishbone.py

@@ -16,9 +16,9 @@ _desc = [
 ]
 
 class Master(Simple):
-	def __init__(self):
+	def __init__(self, name=""):
-		Simple.__init__(self, _desc, False)
+		Simple.__init__(self, _desc, False, name)
 
 class Slave(Simple):
-	def __init__(self):
+	def __init__(self, name=""):
-		Simple.__init__(self, _desc, True)
+		Simple.__init__(self, _desc, True, name)