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cpu/vexriscv: use 32-bit signal for externalResetVector

This commit is contained in:
Florent Kermarrec 2020-01-16 16:20:25 +01:00
parent f2a1673f46
commit 862e784eae
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/cpu/vexriscv/core.py
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@ -238,7 +238,7 @@ class VexRiscv(CPU, AutoCSR):
def set_reset_address(self, reset_address): def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address") assert not hasattr(self, "reset_address")
self.reset_address = reset_address self.reset_address = reset_address
self.cpu_params.update(i_externalResetVector=reset_address) self.cpu_params.update(i_externalResetVector=Signal(32, reset=reset_address))
def add_timer(self): def add_timer(self):
self.submodules.timer = VexRiscvTimer() self.submodules.timer = VexRiscvTimer()