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Lattice NX: Allow up to 320KB of RAM

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David Lattimore 2021-01-06 09:45:08 +11:00
parent 16008d3f3a
commit 875f34f8e2
1 changed files with 3 additions and 4 deletions
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7
litex/soc/cores/ram/lattice_nx.py
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@ -26,13 +26,12 @@ class NXLRAM(Module):
self.bus = wishbone.Interface(width) self.bus = wishbone.Interface(width)
assert width in [32, 64] assert width in [32, 64]
# TODO: allow larger sizes to support Crosslink/NX-17 & Certus
if width == 32: if width == 32:
assert size in [64*kB, 128*kB] assert size in [64*kB, 128*kB, 192*kB, 256*kB, 320*kB]
depth_cascading = size//(64*kB) depth_cascading = size//(64*kB)
width_cascading = 1 width_cascading = 1
if width == 64: if width == 64:
assert size in [128*kB] assert size in [128*kB, 256*kB]
depth_cascading = size//(128*kB) depth_cascading = size//(128*kB)
width_cascading = 2 width_cascading = 2
@ -46,7 +45,7 @@ class NXLRAM(Module):
wren = Signal() wren = Signal()
self.comb += [ self.comb += [
datain.eq(self.bus.dat_w[32*w:32*(w+1)]), datain.eq(self.bus.dat_w[32*w:32*(w+1)]),
If(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d, If(self.bus.adr[14:14+depth_cascading.bit_length()] == d,
cs.eq(1), cs.eq(1),
wren.eq(self.bus.we & self.bus.stb & self.bus.cyc), wren.eq(self.bus.we & self.bus.stb & self.bus.cyc),
self.bus.dat_r[32*w:32*(w+1)].eq(dataout) self.bus.dat_r[32*w:32*(w+1)].eq(dataout)