add address parameter to migIo

This commit is contained in:
Florent Kermarrec 2012-09-13 13:14:27 +02:00
parent f4369c917f
commit 8e86be1a6a
4 changed files with 19 additions and 21 deletions

View File

@ -42,7 +42,7 @@ from migen.bank.description import *
import sys
sys.path.append("../../")
from migScope import trigger, recorder
from migScope import trigger, recorder, migIo
import spi2Csr
from timings import *
@ -65,7 +65,7 @@ dat_width = 16
record_size = 1024
# Csr Addr
CONTROL_ADDR = 0x0000
MIGIO_ADDR = 0x0000
TRIGGER_ADDR = 0x0200
RECORDER_ADDR = 0x0400
@ -74,10 +74,8 @@ RECORDER_ADDR = 0x0400
#==============================================================================
def get():
# Control Reg
control_reg0 = RegisterField("control_reg0", 32, reset=0, access_dev=READ_ONLY)
regs = [control_reg0]
bank0 = csrgen.Bank(regs,address=CONTROL_ADDR)
# migIo
migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO")
# Trigger
term0 = trigger.Term(trig_width)
@ -92,7 +90,7 @@ def get():
# Csr Interconnect
csrcon0 = csr.Interconnect(spi2csr0.csr,
[
bank0.interface,
migIo0.bank.interface,
trigger0.bank.interface,
recorder0.bank.interface
])
@ -107,9 +105,8 @@ def get():
# Led
led0 = Signal(BV(8))
comb += [
led0.eq(control_reg0.field.r[:8])
]
comb += [led0.eq(migIo0.o)]
# Dat / Trig Bus

View File

@ -65,7 +65,7 @@ dat_width = 16
record_size = 1024
# Csr Addr
CONTROL_ADDR = 0x0000
MIGIO_ADDR = 0x0000
TRIGGER_ADDR = 0x0200
RECORDER_ADDR = 0x0400
@ -75,7 +75,7 @@ RECORDER_ADDR = 0x0400
def get():
# migIo
migIo0 = migIo.MigIo(8,"IO")
migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO")
# Trigger
term0 = trigger.Term(trig_width)

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@ -5,11 +5,10 @@ from migen.bank.description import *
class MigIo:
def __init__(self, width, mode = "IO"):
def __init__(self,address, width, mode = "IO"):
self.address = address
self.width = width
self.mode = mode
self.ireg = description.RegisterField("i", 0, READ_ONLY, WRITE_ONLY)
self.oreg = description.RegisterField("o", 0)
if "I" in self.mode:
self.i = Signal(BV(self.width))
self.ireg = description.RegisterField("i", self.width, READ_ONLY, WRITE_ONLY)
@ -18,10 +17,12 @@ class MigIo:
self.o = Signal(BV(self.width))
self.oreg = description.RegisterField("o", self.width)
self.oreg.field.r.name_override = "ouptuts"
self.bank = csrgen.Bank([self.oreg, self.ireg])
self.bank = csrgen.Bank([self.oreg, self.ireg], address=self.address)
def get_fragment(self):
comb = []
comb += [self.ireg.field.w.eq(self.i)]
comb += [self.o.eq(self.oreg.field.r)]
if "I" in self.mode:
comb += [self.ireg.field.w.eq(self.i)]
if "O" in self.mode:
comb += [self.o.eq(self.oreg.field.r)]
return Fragment(comb=comb) + self.bank.get_fragment()

View File

@ -249,7 +249,7 @@ class Trigger:
for object in sorted(objects):
if "_reg" in object:
regs.append(objects[object])
self.bank = csrgen.Bank(regs,address=address)
self.bank = csrgen.Bank(regs,address=self.address)
# Update base addr
for port in self.ports: