Convert -> convert
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1ce4fbdb98
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@ -4,5 +4,5 @@ from migen.corelogic import roundrobin, divider
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r = roundrobin.Inst(5)
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r = roundrobin.Inst(5)
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d = divider.Inst(16)
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d = divider.Inst(16)
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frag = r.get_fragment() + d.get_fragment()
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frag = r.get_fragment() + d.get_fragment()
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o = verilog.Convert(frag, {r.request, r.grant, d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
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o = verilog.convert(frag, {r.request, r.grant, d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
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print(o)
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print(o)
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@ -3,4 +3,4 @@ from migen.flow.ala import *
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act = Divider(32)
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act = Divider(32)
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frag = act.get_control_fragment() + act.get_process_fragment()
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frag = act.get_control_fragment() + act.get_process_fragment()
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print(verilog.Convert(frag))
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print(verilog.convert(frag))
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@ -44,4 +44,4 @@ cpus = [LM32() for i in range(4)]
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frag = Fragment()
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frag = Fragment()
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for cpu in cpus:
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for cpu in cpus:
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frag += cpu.get_fragment()
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frag += cpu.get_fragment()
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print(verilog.Convert(frag, set([cpus[0].inst.ins["interrupt"], cpus[0].inst.outs["I_WE_O"]])))
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print(verilog.convert(frag, set([cpus[0].inst.ins["interrupt"], cpus[0].inst.outs["I_WE_O"]])))
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@ -21,5 +21,5 @@ bank = csrgen.Bank([oreg, ireg])
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f = bank.get_fragment() + inf
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f = bank.get_fragment() + inf
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i = bank.interface
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i = bank.interface
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ofield.dev_r.name = "gpio_out"
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ofield.dev_r.name = "gpio_out"
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v = verilog.Convert(f, {i.d_o, ofield.dev_r, i.a_i, i.we_i, i.d_i, gpio_in})
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v = verilog.convert(f, {i.d_o, ofield.dev_r, i.a_i, i.we_i, i.d_i, gpio_in})
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print(v)
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print(v)
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@ -12,7 +12,7 @@ wishbonecon0 = wishbone.InterconnectShared(
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offset=1)
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offset=1)
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frag = wishbonecon0.get_fragment()
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frag = wishbonecon0.get_fragment()
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v = verilog.Convert(frag, name="intercon", ios={m1.cyc_o, m1.stb_o, m1.we_o, m1.adr_o, m1.sel_o, m1.dat_o, m1.dat_i, m1.ack_i,
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v = verilog.convert(frag, name="intercon", ios={m1.cyc_o, m1.stb_o, m1.we_o, m1.adr_o, m1.sel_o, m1.dat_o, m1.dat_i, m1.ack_i,
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m2.cyc_o, m2.stb_o, m2.we_o, m2.adr_o, m2.sel_o, m2.dat_o, m2.dat_i, m2.ack_i,
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m2.cyc_o, m2.stb_o, m2.we_o, m2.adr_o, m2.sel_o, m2.dat_o, m2.dat_i, m2.ack_i,
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s1.cyc_i, s1.stb_i, s1.we_i, s1.adr_i, s1.sel_i, s1.dat_i, s1.dat_o, s1.ack_o,
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s1.cyc_i, s1.stb_i, s1.we_i, s1.adr_i, s1.sel_i, s1.dat_i, s1.dat_o, s1.ack_o,
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s2.cyc_i, s2.stb_i, s2.we_i, s2.adr_i, s2.sel_i, s2.dat_i, s2.dat_o, s2.ack_o})
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s2.cyc_i, s2.stb_i, s2.we_i, s2.adr_i, s2.sel_i, s2.dat_i, s2.dat_o, s2.ack_o})
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@ -183,7 +183,7 @@ def _printinstances(ns, i, clk, rst):
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r += ");\n\n"
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r += ");\n\n"
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return r
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return r
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def Convert(f, ios=set(), name="top", clk_signal=None, rst_signal=None, ns=None):
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def convert(f, ios=set(), name="top", clk_signal=None, rst_signal=None, ns=None):
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if clk_signal is None:
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if clk_signal is None:
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clk_signal = Signal(name="sys_clk")
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clk_signal = Signal(name="sys_clk")
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ios.add(clk_signal)
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ios.add(clk_signal)
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