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soc/cores/uart: allows 64bits in Stream2Wishbone

This commit is contained in:
Gwenhael Goavec-Merou 2023-10-30 11:03:16 +01:00
parent b5a9106f56
commit 9374196974
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/uart.py
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@ -311,7 +311,7 @@ class Stream2Wishbone(LiteXModule):
# # # # # #
assert data_width in [8, 16, 32] assert data_width in [8, 16, 32]
assert address_width in [8, 16, 32] assert address_width in [8, 16, 32, 64]
cmd = Signal(8, reset_less=True) cmd = Signal(8, reset_less=True)
incr = Signal() incr = Signal()