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Merge pull request #218 from railnova/zynq 

[fix] Slave interface HP0 clk name
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enjoy-digital 2019-07-12 18:00:03 +02:00 committed by GitHub
parent 08772fc0c9 dcf55ad4f3
commit 95796c5b29
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litex/soc/integration/soc_zynq.py
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@ -142,7 +142,7 @@ class SoCZynq(SoCCore):
self.axi_hp0_fifo_ctrl = axi_hp0_fifo_ctrl = Record(axi_fifo_ctrl_layout()) self.axi_hp0_fifo_ctrl = axi_hp0_fifo_ctrl = Record(axi_fifo_ctrl_layout())
self.ps7_params.update( self.ps7_params.update(
# axi hp0 clk # axi hp0 clk
i_M_AXI_HP0_ACLK=ClockSignal("sys"), i_S_AXI_HP0_ACLK=ClockSignal("sys"),
# axi hp0 aw # axi hp0 aw
i_S_AXI_HP0_AWVALID=axi_hp0.aw.valid, i_S_AXI_HP0_AWVALID=axi_hp0.aw.valid,