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fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code

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it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
This commit is contained in:
Florent Kermarrec 2015-03-17 00:25:19 +01:00
parent e946f6e453
commit 9adf3f02f2
2 changed files with 24 additions and 20 deletions
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4
mibuild/generic_platform.py
View file

@ -274,11 +274,11 @@ class GenericPlatform:
def get_verilog(self, fragment, **kwargs):
return self._get_source(fragment, lambda f: verilog.convert(f, self.constraint_manager.get_io_signals(),
return_ns=True, create_clock_domains=False, **kwargs))
return_ns=True, create_clock_domains=False, simulation=False, **kwargs))
def get_edif(self, fragment, cell_library, vendor, device, **kwargs):
return self._get_source(fragment, lambda f: edif.convert(f, self.constraint_manager.get_io_signals(),
cell_library, vendor, device, return_ns=True, **kwargs))
cell_library, vendor, device, return_ns=True, simulation=False, **kwargs))
def build(self, fragment):
raise NotImplementedError("GenericPlatform.build must be overloaded")

8
migen/fhdl/verilog.py
View file

@ -175,9 +175,10 @@ def _printheader(f, ios, name, ns):
r += "\n"
return r
def _printcomb(f, ns, display_run):
def _printcomb(f, ns, simulation, display_run):
r = ""
if f.comb:
if simulation:
# Generate a dummy event to get the simulator
# to run the combinatorial process once at the beginning.
syn_off = "// synthesis translate_off\n"
@ -194,6 +195,7 @@ def _printcomb(f, ns, display_run):
if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
r += "assign " + _printnode(ns, _AT_BLOCKING, 0, g[1][0])
else:
if simulation:
dummy_d = Signal(name_override="dummy_d")
r += "\n" + syn_off
r += "reg " + _printsig(ns, dummy_d) + ";\n"
@ -205,6 +207,7 @@ def _printcomb(f, ns, display_run):
for t in g[0]:
r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
r += _printnode(ns, _AT_NONBLOCKING, 1, g[1])
if simulation:
r += syn_off
r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
r += syn_on
@ -295,6 +298,7 @@ def convert(f, ios=None, name="top",
return_ns=False,
special_overrides=dict(),
create_clock_domains=True,
simulation=True,
display_run=False):
if not isinstance(f, _Fragment):
f = f.get_fragment()
@ -324,7 +328,7 @@ def convert(f, ios=None, name="top",
r = "/* Machine-generated using Migen */\n"
r += _printheader(f, ios, name, ns)
r += _printcomb(f, ns, display_run)
r += _printcomb(f, ns, simulation, display_run)
r += _printsync(f, ns)
r += _printspecials(special_overrides, f.specials - lowered_specials, ns)
r += _printinit(f, ios, ns)