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remove verilog and move mxcrg.v to misoclib/mxcrg
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2 changed files with 1 additions and 1 deletions
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@ -68,7 +68,7 @@ INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
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PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
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PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
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""")
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""")
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platform.add_source_dir(os.path.join("verilog", "mxcrg"))
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platform.add_source_dir(os.path.join("misoclib", "mxcrg"))
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class MiniSoC(BaseSoC):
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class MiniSoC(BaseSoC):
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csr_map = {
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csr_map = {
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