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examples/corelogic_conv: use two dividers

This commit is contained in:
Sebastien Bourdeauducq 2012-01-16 19:38:39 +01:00
parent 4c85d921b3
commit a1043d11c0
1 changed files with 7 additions and 5 deletions
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12
examples/corelogic_conv.py
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@ -1,8 +1,10 @@
from migen.fhdl import verilog
from migen.corelogic import roundrobin, divider
from migen.corelogic import divider
r = roundrobin.Inst(5)
d = divider.Inst(16)
frag = r.get_fragment() + d.get_fragment()
o = verilog.convert(frag, {r.request, r.grant, d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
d1 = divider.Inst(16)
d2 = divider.Inst(16)
frag = d1.get_fragment() + d2.get_fragment()
o = verilog.convert(frag, {
d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i})
print(o)