use ram for Sum
This commit is contained in:
parent
f4cac2c102
commit
a7d85af25b
|
@ -144,25 +144,31 @@ class Timer:
|
||||||
return Fragment(comb, sync)
|
return Fragment(comb, sync)
|
||||||
|
|
||||||
class Sum:
|
class Sum:
|
||||||
def __init__(self,size=4,pipe=False):
|
def __init__(self,width=4,pipe=False):
|
||||||
self.size = size
|
self.width = width
|
||||||
self.pipe = pipe
|
self.pipe = pipe
|
||||||
self.i = Array(Signal() for j in range(self.size))
|
|
||||||
|
self.i = Signal(BV(self.width))
|
||||||
self._o = Signal()
|
self._o = Signal()
|
||||||
self.o = Signal()
|
self.o = Signal()
|
||||||
|
self._lut_port = MemoryPort(adr=self.i, dat_r=self._o)
|
||||||
|
|
||||||
self.prog = Signal()
|
self.prog = Signal()
|
||||||
self.prog_dat = Signal(BV(16))
|
self.prog_adr = Signal(BV(width))
|
||||||
|
self.prog_dat = Signal()
|
||||||
|
self._prog_port = MemoryPort(adr=self.prog_adr, we=self.prog, dat_w=self.prog_dat)
|
||||||
|
|
||||||
|
self._mem = Memory(1, 2**self.width, self._lut_port, self._prog_port)
|
||||||
|
|
||||||
def get_fragment(self):
|
def get_fragment(self):
|
||||||
comb = []
|
comb = []
|
||||||
sync = []
|
sync = []
|
||||||
comb +=[self.o.eq(optree("|", [self.i[j] for j in range(self.size)]))]
|
memories = [self._mem]
|
||||||
if self.pipe:
|
if self.pipe:
|
||||||
sync += [self.o.eq(self._o)]
|
sync += [self.o.eq(self._o)]
|
||||||
else:
|
else:
|
||||||
comb += [self.o.eq(self._o)]
|
comb += [self.o.eq(self._o)]
|
||||||
return Fragment(comb=comb,sync=sync)
|
return Fragment(comb=comb,sync=sync,memories=memories)
|
||||||
|
|
||||||
|
|
||||||
class Trigger:
|
class Trigger:
|
||||||
|
|
Loading…
Reference in New Issue