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soc/cores/uart:Stream2Wishbone: remove no more needed data_width/address_width equality test

This commit is contained in:
Gwenhael Goavec-Merou 2022-04-15 17:43:50 +02:00
parent 3cb34e7951
commit a988712974
1 changed files with 0 additions and 2 deletions
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litex/soc/cores/uart.py
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@ -312,8 +312,6 @@ class Stream2Wishbone(Module):
# # # # # #
assert data_width == address_width
cmd = Signal(8, reset_less=True) cmd = Signal(8, reset_less=True)
incr = Signal() incr = Signal()
length = Signal(8, reset_less=True) length = Signal(8, reset_less=True)