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wishbone/SRAM: make read_only emited verilog code compatible with all tools 

Quartus was not able to implement ROM correctly, see #228
This commit is contained in:
Florent Kermarrec 2019-08-05 09:08:56 +02:00
parent ce5c58592b
commit a9fe2788a2
1 changed files with 2 additions and 1 deletions
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3
litex/soc/interconnect/wishbone.py
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@ -653,7 +653,8 @@ class SRAM(Module):
### ###
# memory # memory
port = self.mem.get_port(write_capable=not read_only, we_granularity=8) port = self.mem.get_port(write_capable=not read_only, we_granularity=8,
mode=READ_FIRST if read_only else WRITE_FIRST)
self.specials += self.mem, port self.specials += self.mem, port
# generate write enable signal # generate write enable signal
if not read_only: if not read_only: