Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #1074 from navan93/use-ibex-main-repo 

Use ibex main repo
This commit is contained in:
enjoy-digital 2021-10-23 17:24:04 +02:00 committed by GitHub
parent 68b67af1bd a7a746473d
commit adc3aecc56
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 15 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
litex/soc/cores/cpu/ibex/core.py
View File

@ -189,8 +189,20 @@ class Ibex(CPU):
@staticmethod
def add_sources(platform):
opentitandir = get_data_mod("misc", "opentitan").data_location
ibexdir = os.path.join(os.path.join(opentitandir, "hw", "vendor", "lowrisc_ibex"))
ibexdir = get_data_mod("cpu", "ibex").data_location
platform.add_verilog_include_path(os.path.join(ibexdir, "rtl"))
platform.add_verilog_include_path(os.path.join(ibexdir,
"vendor", "lowrisc_ip", "dv", "sv", "dv_utils")
)
platform.add_verilog_include_path(os.path.join(ibexdir,
"vendor", "lowrisc_ip", "ip", "prim", "rtl")
)
platform.add_source(os.path.join(ibexdir, "syn", "rtl", "prim_clock_gating.v"))
platform.add_sources(os.path.join(ibexdir, "vendor", "lowrisc_ip", "ip", "prim", "rtl"),
"prim_alert_pkg.sv",
"prim_assert.sv",
"prim_ram_1p_pkg.sv",
)
platform.add_sources(os.path.join(ibexdir, "rtl"),
"ibex_pkg.sv",
"ibex_alu.sv",
@ -211,23 +223,8 @@ class Ibex(CPU):
"ibex_register_file_fpga.sv",
"ibex_wb_stage.sv",
"ibex_core.sv",
#"ibex_top.sv" FIXME.
"ibex_top.sv"
)
# FIXME: Patch ibex_top.sv to fix missing import.
if not os.path.exists("ibex_top.sv"):
# Get ibex_top source.
os.system("cp {src} {dst}".format(src=os.path.join(ibexdir, "rtl", "ibex_top.sv"), dst="ibex_top.sv"))
# FIXME: Patch ibex_top
os.system(f"patch -p0 < {os.path.dirname(os.path.realpath(__file__))}/ibex_top.patch")
platform.add_source("ibex_top.sv")
platform.add_source(os.path.join(ibexdir, "syn", "rtl", "prim_clock_gating.v"))
platform.add_sources(os.path.join(opentitandir, "hw", "ip", "prim", "rtl"),
"prim_alert_pkg.sv",
"prim_assert.sv"
)
platform.add_verilog_include_path(os.path.join(opentitandir, "hw", "ip", "prim", "rtl"))
platform.add_verilog_include_path(os.path.join(opentitandir, "hw", "dv", "sv", "dv_utils"))
def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")