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interconnect/axi/AXIArbiter: valid also needs to be filtered. 

Fixes un-sollicited valids on masters.
This commit is contained in:
Florent Kermarrec 2022-08-05 11:20:25 +02:00
parent a286d77e01
commit ae8deda186
2 changed files with 6 additions and 6 deletions
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6
litex/soc/interconnect/axi/axi_full.py
View File

@ -359,7 +359,7 @@ class AXIArbiter(Module):
"""
def __init__(self, masters, target):
self.submodules.rr_write = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
self.submodules.rr_read = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
self.submodules.rr_read = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
def get_sig(interface, channel, name):
return getattr(getattr(interface, channel), name)
@ -378,8 +378,8 @@ class AXIArbiter(Module):
source = get_sig(target, channel, name)
for i, m in enumerate(masters):
dest = get_sig(m, channel, name)
if name == "ready":
self.comb += dest.eq(source & (rr.grant == i))
if name in ["valid", "ready"]:
self.comb += If(rr.grant == i, dest.eq(source))
else:
self.comb += dest.eq(source)

6
litex/soc/interconnect/axi/axi_lite.py
View File

@ -603,7 +603,7 @@ class AXILiteArbiter(Module):
"""
def __init__(self, masters, target):
self.submodules.rr_write = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
self.submodules.rr_read = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
self.submodules.rr_read = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
def get_sig(interface, channel, name):
return getattr(getattr(interface, channel), name)
@ -622,8 +622,8 @@ class AXILiteArbiter(Module):
source = get_sig(target, channel, name)
for i, m in enumerate(masters):
dest = get_sig(m, channel, name)
if name == "ready":
self.comb += dest.eq(source & (rr.grant == i))
if name in ["valid", "ready"]:
self.comb += If(rr.grant == i, dest.eq(source))
else:
self.comb += dest.eq(source)