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soc_core: use fixed 16MB CSR address space

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Using too small CSR address space cause a regression on PCIe SoC, this would
need to be understood if we want to reduce CSR address space under 16MB.
This commit is contained in:
Florent Kermarrec 2019-07-10 10:37:32 +02:00
parent 68a503174c
commit b0192e5f8b
1 changed files with 2 additions and 1 deletions
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litex/soc/integration/soc_core.py
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@ -298,7 +298,8 @@ class SoCCore(Module):
self.add_csr_master(self.wishbone2csr.csr)
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.config["CSR_ALIGNMENT"] = csr_alignment
self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 2**(csr_address_width + 2))
assert 2**(csr_address_width + 2) <= 0x1000000
self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 0x1000000)
# Add UART
if with_uart: