soc_core: add UART bridge support (simplify having to do it externally)

2020-01-31 15:12:18 +01:00 · 2020-01-31 15:12:18 +01:00 · b69f2993e4
parent 7a6c04db9e
commit b69f2993e4
1 changed files with 3 additions and 0 deletions
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@ -243,6 +243,9 @@ class SoCCore(Module):
                self.submodules.uart = uart.UART()
                if uart_name == "stub":
                    self.comb += self.uart.sink.ready.eq(1)
+            elif uart_name == "bridge":
+                self.submodules.uart = uart.UARTWishboneBridge(platform.request("serial"), clk_freq, uart_baudrate)
+                self.add_wb_master(self.uart.wishbone)
            elif uart_name == "crossover":
                self.submodules.uart = uart.UARTCrossover()
            else: