Merge pull request #1486 from alanvgreen/terms
litex/soc: update API to avoid unfortunate terms
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commit
b8e007540c
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@ -408,6 +408,9 @@ class SoCBusHandler(LiteXModule):
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colorer(name, color="underline"),
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colorer(name, color="underline"),
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colorer("added", color="green")))
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colorer("added", color="green")))
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def add_controller(self, name=None, controller=None):
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self.add_master(self, name=name, master=controller)
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def add_slave(self, name=None, slave=None, region=None):
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def add_slave(self, name=None, slave=None, region=None):
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no_name = name is None
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no_name = name is None
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no_region = region is None
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no_region = region is None
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@ -440,6 +443,9 @@ class SoCBusHandler(LiteXModule):
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colorer(name, color="underline"),
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colorer(name, color="underline"),
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colorer("added", color="green")))
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colorer("added", color="green")))
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def add_peripheral(self, name=None, peripheral=None, region=None):
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self.add_slave(self, name=name, slave=peripheral, region=region)
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def get_address_width(self, standard):
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def get_address_width(self, standard):
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standard_from = self.standard
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standard_from = self.standard
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standard_to = standard
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standard_to = standard
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@ -149,7 +149,12 @@ class InterconnectPointToPoint(Module):
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class Arbiter(Module):
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class Arbiter(Module):
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def __init__(self, masters, target):
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def __init__(self, masters=None, target=None, controllers=None):
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assert target is not None
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assert (masters is not None) or (controllers is not None)
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if controllers is not None:
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masters = controllers
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self.submodules.rr = roundrobin.RoundRobin(len(masters))
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self.submodules.rr = roundrobin.RoundRobin(len(masters))
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# mux master->slave signals
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# mux master->slave signals
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