verilog: fix unary operator conversion

2011-12-08 21:15:24 +01:00 · 2011-12-08 21:15:24 +01:00 · bf021efa2b
parent 78f18ad593
commit bf021efa2b
1 changed files with 1 additions and 1 deletions
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@ -23,7 +23,7 @@ def _printexpr(ns, node):
 	elif isinstance(node, Operator):
 		arity = len(node.operands)
 		if arity == 1:
-			r = self.op + _printexpr(ns, node.operands[0])
+			r = node.op + _printexpr(ns, node.operands[0])
 		elif arity == 2:
 			r = _printexpr(ns, node.operands[0]) + " " + node.op + " " + _printexpr(ns, node.operands[1])
 		else: