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verilog: fix unary operator conversion

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Sebastien Bourdeauducq 2011-12-08 21:15:24 +01:00
parent 78f18ad593
commit bf021efa2b
1 changed files with 1 additions and 1 deletions
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2
migen/fhdl/verilog.py
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@ -23,7 +23,7 @@ def _printexpr(ns, node):
elif isinstance(node, Operator): elif isinstance(node, Operator):
arity = len(node.operands) arity = len(node.operands)
if arity == 1: if arity == 1:
r = self.op + _printexpr(ns, node.operands[0]) r = node.op + _printexpr(ns, node.operands[0])
elif arity == 2: elif arity == 2:
r = _printexpr(ns, node.operands[0]) + " " + node.op + " " + _printexpr(ns, node.operands[1]) r = _printexpr(ns, node.operands[0]) + " " + node.op + " " + _printexpr(ns, node.operands[1])
else: else: