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liteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce ressource usage with MII phy)

This commit is contained in:
Florent Kermarrec 2015-07-05 22:45:53 +02:00
parent c1ca928ec2
commit c100ef6406
1 changed files with 7 additions and 2 deletions
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9
misoclib/com/liteeth/core/mac/core/__init__.py
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@ -1,6 +1,7 @@
from misoclib.com.liteeth.common import * from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.core.mac.core import gap, preamble, crc, padding, last_be from misoclib.com.liteeth.core.mac.core import gap, preamble, crc, padding, last_be
from misoclib.com.liteeth.phy.sim import LiteEthPHYSim from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
from misoclib.com.liteeth.phy.mii import LiteEthPHYMII
class LiteEthMACCore(Module, AutoCSR): class LiteEthMACCore(Module, AutoCSR):
@ -80,8 +81,12 @@ class LiteEthMACCore(Module, AutoCSR):
rx_pipeline += [rx_converter] rx_pipeline += [rx_converter]
# Cross Domain Crossing # Cross Domain Crossing
tx_cdc = AsyncFIFO(eth_phy_description(dw), 64) if isinstance(phy, LiteEthPHYMII):
rx_cdc = AsyncFIFO(eth_phy_description(dw), 64) fifo_depth = 8
else:
fifo_depth = 64
tx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
rx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"}) self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"}) self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})