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soc/cores/clock/efinix: allowing to specify LVDS input refclk name (Trion)

This commit is contained in:
Gwenhael Goavec-Merou 2023-11-14 21:06:25 +01:00
parent f41ae88d1c
commit c8a9f205e0
1 changed files with 2 additions and 1 deletions
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3
litex/soc/cores/clock/efinix.py
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@ -55,7 +55,7 @@ class EFINIXPLL(LiteXModule):
self.comb += self.platform.add_iface_io(self.name + "_rstn").eq(~self.reset)
self.comb += self.locked.eq(self.platform.add_iface_io(self.name + "_locked"))
def register_clkin(self, clkin, freq, name="", lvds_input=False):
def register_clkin(self, clkin, freq, name="", refclk_name="", lvds_input=False):
block = self.platform.toolchain.ifacewriter.get_block(self.name)
block["input_clock_name"] = self.platform.get_pin_name(clkin)
@ -81,6 +81,7 @@ class EFINIXPLL(LiteXModule):
block["input_clock"] = "EXTERNAL" if not lvds_input else "LVDS_RX"
block["input_clock_pad"] = pin_name
block["input_refclk_name"] = refclk_name
block["resource"] = pll_res
block["clock_no"] = clock_no
self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no))